MIPS is a major player in the RISC-V arena with an array of IP from hard real-time cores to those supporting artificial-intelligence (AI) large language models (LLMs). A typical customer will incorporate these cores into their custom design.

It’s possible to evaluate a design via simulation but having real hardware is useful, which is where the suite of reference designs comes into play. These include the MIPS Actus-1, MIPS Acies-1, and MIPS Aegis-1 that incorporates RISC-V profiles like RMV32 and RVA23.

The platforms are a collection of modules, M.2 cards, and motherboards. The designs do focus on supporting physical AI and robotics, but they can be utilized for any embedded application. The systems aim for developers that want to evaluate the platforms or use them in prototypes rather than employing them within a final product.

MIPS Actus-1 for Real Time Physical AI

The MIPS Actus-1 is a module designed to handle real-time motor control and communication (Fig. 1). It is built around a pair of MIPS Atlas M8500 real-time, RMV23 profile, RISC-V cores with an ARC VPX 512-bit vector processing unit. The module is built using GlobalFoundries’ FDX FD-SOI technology. It uses MRAM for on-chip, non-volatile storage. The system targets applications that require SO 26262 and ISO 21434​​ certification.

The system is designed to handle field-oriented control (FOC) by including 100-ps-class high-resolution PWM along with a sigma-delta analog-to-digital converter (ADC). The gigabit Ethernet port is tied to a three-port switch, which supports time-sensitive networking (TSN). The system also supports interfaces such as USB, CAN-FD, SPI, and I2C.

MIPS Acies-1 for Intelligent Physical AI

AI support can be added using the Acies-1 M.2 module (Fig. 2) with the MIPS Atlas S8200, a RISC-V RVA23 platform with RVV (RISC-V vector extensions) and VME (vector matrix extensions) capability. It can handle LLMs like Llama.cpp and Qwen as well as vision-language-action (VLA) models. The module delivers 50 TOPS of performance using eight cores with a bandwidth of over 50 GB/s while using only 10 W of power. It supports integer and floating-point weights including FP4 support.

The AI acceleration is supported by MIPS’ Atlas SDK and Graph Performance Simulator. This includes an Intermediate Representation Execution Environment-based (IREE) Multi-Level Intermediate Representation (MLIR) compiler that handles TensorFlow, PyTorch, and ONNX.

MIPS Actus-1 for Safety-Critical Physical AI

The Actus-1 and Acies-1 focus on real-time motor control and AI acceleration, while the Actus-1 is the central controller that typically runs an operating system like Linux. It’s designed to handle agentic workloads itself using a multi-core ARC-V RPX-500 processor (Fig. 3). The Actus-1 also includes an Atlas M8500 safety processor, an ARC RHX-100 security processor, and an Atlas S8200 neural processing unit (NPU). It can support standards like ISO 26262, ISO 21434, and the European Union’s CRA.

The Ethernet support is managed by an Atlas I8500 integer RISC-V core. It also supports TSN. The chip works with PCI Express, USB, SPI and other standard serial and parallel interfaces. Furthermore, the system handles AI applications and can be used to manage a physical AI system.

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