SiFive today announced it has raised $400 million in an oversubscribed Series G funding round to ‘accelerate its high-performance data center roadmap’. This round, led by Atreides Management—whose other recent investments include Positron, Mythic, and Cerebras, as well as previously in Axiado, Astera Labs, and Enfabrica—brings SiFive’s total funding to date at around $970 million, with a post-money valuation of $3.65 billion. This compares with a $2.5 billion valuation in 2022, when it raised $175 million in its Series F round.

SiFive's Jack Kang
SiFive’s Jack Kang

This latest funding highlights huge demand for agentic AI workloads, and subsequently, as we heard from Arm in full detail just two weeks ago, the huge demand for CPUs. In a written response to EE Times, Jack Kang, SiFive’s SVP for business development and sales, said, “As reported widely in the media, data center customers are seeing an outsized surge in agentic AI compute demand. SiFive expects future data centers to include a variety of ISAs, including x86, Arm, and RISC-V. The desire to accelerate RISC-V and achieve key benefits from workload-optimized IP with SiFive is a key driver of this oversubscribed round. We don’t need any competitor to “lose” in order for us to be wildly successful here.”

While Kang said nobody needs to lose, his chairman and CEO, Patrick Little, said in the official news announcement today that RISC-V is the only architecture that will allow data center customers to differentiate. In the prepared remarks, Little noted, “Hyperscale customers have made it very clear that it is time to accelerate the availability of open standard alternatives for the data center. Their consistent ask is for customizable CPU solutions in IP form that will enable them to meaningfully differentiate their data center compute solutions. RISC-V is the only architecture that truly delivers on these requirements. As the industry urgently evolves toward agentic AI, SiFive is doubling down on the data center. By collaborating with our data center customers, we are uniquely positioned to capture a substantial portion of the tremendous agentic AI opportunity.”

The low-power argument for RISC-V CPUs in agentic AI models

SiFive goes on to explain the importance of CPUs in orchestrating complex system-level coordination tasks that GPUs and AI accelerators aren’t designed to handle efficiently. The company said that as AI evolves toward more complex agentic models, efficient CPU performance is critical to expanding compute capacity within existing power envelopes. It added, “SiFive enables this transition by replacing complex, power-hungry legacy architectures with modern RISC-V CPUs that are inherently lower power. RISC-V integrates scalar, vector, and matrix compute into a single, standards-based interface that helps customers scale rapidly, significantly accelerating hardware development to match the speed of AI innovation.”

SiFive added a quote from The Futurum Group’s CEO and chief analyst, Dan Newman, who emphasized the significance of RISC-V and the re-emergence of CPU interest for data centers. Newman said, “The CPU is suddenly exciting again, especially for applications in the data center. SiFive spotted this trend early and is well-positioned to benefit as the industry evolves. While legacy architectures are the current incumbents, we are seeing major chip and hyperscale companies envision a future with RISC-V in the data center. This $400 million investment round signals a pivotal shift toward RISC-V as a primary contender for high-performance computing, offering a flexible, efficient alternative to legacy architectures and bringing the strength of a global ecosystem to drive new solutions.”

Patrick Little SiFive CEO
SiFive’s Patrick Little

We did ask SiFive about some of their customers driving the company’s demand in data centers. Given that Arm’s CPU was largely driven by co-development with Meta, EE Times thought there may be a similar lead customer driving SiFive’s roadmap, too. But SiFive has always maintained that it had a number of customers without ever naming them. In our 2022 interview with Patrick Little, the CEO said that adoption of the company’s Performance and Intelligence line processors had “wildly exceeded” their expectations. He said, “Almost every customer we spoke to said there’s a mandate from their boards to diversify their processor base. While we may have been focused previously on simple embedded designs, we’re now seeing a shift where we are targeting the center of the customer’s requirements for intelligent designs.”

Little also noted at the time that SiFive’s revenue mix had shifted from being almost entirely driven by embedded products to being increasingly led by high-performance products. In this week’s written response to EE Times, Kang said, “SiFive is not disclosing any specific customer details as part of this announcement. But we can disclose that we are working with several hyperscaler customers on future high-performance CPU design requirements, all of whom are existing customers of SiFive RISC-V IP in other performance segments. That is to say, we have earned our way into this space with multiple generations of successful commercial shipments.”

Kang added, “We are not commenting on current traction/revenue for existing data center solutions at this point. But we will disclose that our previously announced datacenter-focused products, the P870-D and XM, are both in customer silicon with a data center customer right now.”

Roadmaps and IPO

In our 2022 interview with Little after SiFive’s Series F round, the company’s CEO said the company was looking to IPO within a year. Hence, we thought it appropriate to ask about the product roadmap and exit plans. Kang told EE Times, “We are not disclosing any roadmap specifics, other than we are planning for the highest point of data center performance, and this investment is specifically to accelerate these efforts over multiple generations of products. These will also be more than just CPU IP; we will be providing customers with full IP solutions, including power management, interconnect, security, and so on.”

Kang added, “Near term, the data center opportunity is an exciting milestone to focus on as we march toward IPO readiness. We have no new disclosures on IPO timing at this point.” Clearly, the $400 million funding round signals that investors are prepared to wait at least a couple more years to see how the high-value data center market develops for SiFive in terms of growth and revenue.

Not the only RISC-V targeting data centers

One of the other key RISC-V players targeting data centers was Ventana Micro Systems, which was acquired in December 2025 by Qualcomm. Since the announcement, there has been limited further information on where Ventana’s Veyron processor IP will end up. In late 2024, however, Ventana said that its Veyron V2 would start shipping in 2025 to address demand in data centers for AI and domain-specific computing. Back in 2022, Ventana CEO and founder Balaji Baktha told EE Times that the level of excitement for Ventana’s solution was very strong in hyperscalers, particularly in China, but also in the U.S. Meanwhile, in Europe, there was significant interest for RISC–V chiplets in high–performance computing.

Other RISC-V news this week

While we talk about RISC-V, two other notable announcements came in this week—one from Semidynamics and the other from Codasip.

Semidynamics, a company developing memory-centric AI infrastructure for large-scale inference, announced a strategic investment from SK Hynix. The official announcement said the investment ‘reflects a shared conviction that memory architecture, not compute alone, will define the economics of next-generation AI inference, where cost per token is the metric that matters’.

As large language models scale, and as agentic, multi-turn workloads demand persistent context across longer inference sessions, system performance is increasingly constrained by memory capacity and data movement rather than raw compute. Semidynamics said it is capable of delivering multiples of the memory capacity available in conventional HBM-based inference systems, hence supporting larger models, larger KV-caches, and larger contexts. These three features, it said, enable more users per rack, directly leading to lower cost per token.

Codasip announced this week a ‘strategic pivot’ to building processor IP and chips for cybersecurity, incorporating CHERI (Capability Hardware Enhanced RISC Instructions) technology. As a result of this pivot, it is divesting its low-end RISC-V processor design business to a public U.S. semiconductor company. The news announcement said, “As part of the divestiture, the acquiring company will also take a broad license to Studio, Codasip’s processor EDA tool that allows customization of Codasip processor cores. The transaction is planned to close in a month.”

However, the announcement did not disclose the identity of the publicly listed U.S. company, and none of the sources consulted were able to confirm the buyer.