Amelia’s Weekly Fish Fry – Episode 707

Speaker: Shankaran Janardhanan, Senior Vice President of Photonics and RF Business at GlobalFoundries

Publication date: November 13, 2026

Amelia Dalton: Hello there, everyone! Welcome to episode number 707 of this here electronic engineering podcast called Amelia’s Weekly Fish Fry, brought to you by eejournal.com and written, produced, and hosted by yours truly, Amelia Dalton.

My guest this week is Shankaran Janardhanan, Senior Vice President of Photonics and RF Business at GlobalFoundries.

Shankaran and I are talking all about the analog and RF side of AI infrastructure, the critical role that high-speed interconnects play in these types of systems, and why silicon germanium is key to pushing past the limits of traditional CMOS.

So, without further ado, please welcome Shankaran to Fish Fry!

Hello! Thank you so much for joining me.

Shankaran Janardhanan: Thank you, Amelia. It’s a pleasure to be talking to you.

Amelia Dalton: Excellent! Okay, so for listeners who may not think about the analog side of AI infrastructure very often, can you explain why the real interconnect challenge is increasingly happening in the analog and RF domain rather than in the digital logic itself?

Shankaran Janardhanan: Oh man, absolutely. First of all, thank you for taking the time to meet with me, Amelia.

For users who don’t know a lot about GlobalFoundries, let me introduce Global very quickly. GlobalFoundries is a differentiated technology solutions provider, especially for differentiated technologies brought together at manufacturing, with globally distributed manufacturing at scale. We have manufacturing locations in Europe, Asia, and the United States.

Going to your question about why the analog part of the domain has become much more important, especially as the AI data center rollout continues to progress, the way we want to think about it is that it’s all about closing the entire link budget at the optical module level.

The constraint in AI has moved from compute to connectivity. And when it moves from compute to connectivity, it moves into the realm of differentiated technologies that are non-CMOS-based.

For example, the DSP, or digital signal processor, today is in some 7-nanometer technology, so it’s actually in leading-edge nodes, if you will. But if you’re looking at the transimpedance amplifiers and the drivers that are needed to close the link budget, they tend to demand much higher-frequency technologies and higher-bandwidth technologies. That’s where technologies like silicon germanium come into play.

So that is where the requirements become a lot more stringent, and it moves from, I would call, the digital domain to the analog and RF domain.

Amelia Dalton: Absolutely. Okay, so we keep hearing about this push toward 200 gigabits per second and beyond per lane. What actually starts to break down in traditional CMOS approaches once you reach those data rates, and how is silicon germanium becoming an important technology for pushing that performance further?

Shankaran Janardhanan: Yeah, no, absolutely. That’s actually a great question.

As the market moves from 100 gig per lane to 200 gig per lane, 200 gig per lane is actually ramping up right now, especially in scale-out architectures. The future is actually expected to head toward 400 gig per lane in scale-out and scale-up as well.

As you move from trying to increase data rates, you start to get into signal integrity problems. You start to get into being able to close the link budget at the desired bit error rate.

The bit error rate is sort of a key figure of merit at the system level that needs to be closed. In order to be able to do that, you need a very high-frequency technology, a high-speed, high-frequency technology that operates at really good power efficiency at these data rates.

And that is where CMOS can’t really keep up. That is where silicon germanium actually shines very nicely.

Silicon germanium technology is built on a vertical device, and the NPN is actually a vertical device. That basically lends itself very nicely to building very high-frequency, high FT and Fmax technology at very low noise figure.

So, if you’re trying to optimize the design over a wide bandwidth at a very low noise figure, silicon germanium is sort of the right technology of choice, which is where CMOS will struggle to keep up.

Amelia Dalton: So, when we talk about AI data centers, the conversation often focuses on GPUs, accelerators, and the compute itself. But how important are the underlying high-speed interconnects in determining how much of that compute we can actually use, and where are the bottlenecks showing up today?

Shankaran Janardhanan: Okay, that’s actually a good question.

The way we want to think about it is that the constraint in AI has shifted from compute to connectivity and power.

Where the constraint has actually moved, especially in the connectivity realm, is the fact that you need to support the evolving architectures in either scale-up, scale-out, or scale-across.

All of these three different networking architectures need to be able to support all of the bandwidth requirements. You need to be able to support wavelength division multiplexing, for example, and so forth.

All of this actually requires cutting-edge technologies that are not CMOS-based, which is where technologies like silicon germanium and so forth come in.

That answers your question about where the constraint has moved into connectivity.

In terms of the bottlenecks, I would say the bottleneck actually comes in being able to connect all of the GPUs together to be able to perform as a single computing system.

The ability to perform as a single computing system means that data has to be transferred between these GPUs within the rack, or data has to be transmitted across the racks in a seamless fashion.

It has to be done in a very low-latency fashion, and it has to be done in a way where there is very high signal integrity.

In order to be able to do that, you need high-frequency technologies. You need high-frequency technologies that also lend themselves to very low noise figures over wider bandwidths.

That’s how the constraint gets solved. It’s actually a very important constraint at a system level that needs to be addressed with technologies like silicon germanium.

Amelia Dalton: GlobalFoundries is expanding its silicon germanium capacity. How does this manufacturing expansion reflect broader trends across AI networks?

Shankaran Janardhanan: No, absolutely. I think if you look at what’s happening in the hyperscaler spend at a very high level, the hyperscalers are spending a significant amount of money.

If you’re looking at what the hyperscalers have spent in the last couple of years, I think it was like $400 billion, growing to about $800 billion across the different hyperscalers, and expected to cross over a trillion dollars in hyperscaler spend.

As hyperscaler spend continues to accelerate, we need to be able to support the data center rollout.

In order to be able to support it, I just talked about how silicon germanium as a technology becomes a key component of being able to cross the electrical link, the electro-optical link in optical modules.

All of these data centers need to be connected together across multiple racks, and even within the racks, they need to be connected together.

This is where technologies like silicon germanium come in. We not only need cutting-edge technologies, but we also need cutting-edge technologies brought to the market at scale.

That is where the expansion of capacity comes into play, and that is where GlobalFoundries is continuing to invest very heavily in our silicon germanium capacity expansion, whether it’s in our U.S. facility or whether we do it in Singapore.

So, I think this is in response to all of the data center spend that we are seeing and being able to support that rollout.

Amelia Dalton: So, if we look a few years down the road, where do you think the next big interconnect challenge is going to emerge? Are we talking about even higher speeds per lane, greater power efficiency, optical integration, or something else entirely?

Shankaran Janardhanan: No, actually, it’s an intriguing question to think about where this is all heading.

I would say I think this is going to head in a couple of different vectors.

If you’re looking at scale-out networks, as they continue to accelerate, I think the data rates are going to continue to increase from 200 gig per lane to 400 gig per lane. That means that the constraints on the link budget and the closure of the link budget become even more important.

The bit error rate figure of merit is going to become even more stringent. And that is where the next generation of silicon germanium technologies will need to be brought to bear.

So, I’m talking about higher FTs, higher Fmaxes, greater than 500 gig, greater than 600 gig Fmaxes. Technologies need to be brought into the market so that way they can address that requirement.

That is one area of evolution that we are observing from a scale-out architecture standpoint.

From a scale-up architecture standpoint, I would say the market is going to go through a different sort of growth vector. It is shifting from copper to optical.

This is where it is actually shifting into dense wavelength division multiplexing. So, the modulation schemes that are being used even in scale-up are still probably going to be 50 gigabit per lane NRZ, growing to 100 gigabit per lane NRZ, and so forth.

I would say that market is going to require a different sort of form factor that needs to be brought in to solve it.

It could move from, for example, pluggables to co-packaged optics, which is going to bring together a different set of constraints.

For example, in co-packaged optics, you need modulators that have a very small footprint. This is where microring resonators, for example, come into play as well.

So, it depends on how the architectures are evolving between scale-out and scale-up and what technologies we bring to bear.

It’s going to vary between higher-performance silicon germanium technologies to close the electrical link, and different sorts of modulator materials that we are assessing.

The market will need materials like thin-film lithium niobate, barium titanate, and so forth for scale-out architectures. From a scale-up standpoint, it will require different sorts of form factors as it moves from copper to optical.

Amelia Dalton: All right! Well, Shankaran, it’s time for your off-the-cuff question. Are you ready?

Shankaran Janardhanan: I’m ready. Go ahead!

Amelia Dalton: All right! So, if you could have one meal right now, it doesn’t matter if it’s on the other side of the world and you need a passport to get there, what would you have?

Shankaran Janardhanan: That’s a good question. I would like to have a very nice Indian masala dosa. If I could have that, I would get on a flight and go there and have it.

Amelia Dalton: I love it! That sounds delicious.

Awesome! Well, this was a pleasure speaking with you. Thank you so much for joining me.

Shankaran Janardhanan: All right. Thank you, Amelia. It was a pleasure talking to you as well.

Amelia Dalton: Well, folks, that’s all I’ve got for this week’s Fish Fry.

If you’d like even more information about the topics covered in today’s show, I’ve included a couple of links below the player on this week’s Fish Fry page on eejournal.com and in the description for this week’s YouTube episode as well.

By the way, have you connected with EE Journal on social media yet? Well, you should! You can find us on LinkedIn, BlueSky Social, and Mastodon.

Don’t forget about our YouTube channel at youtube.com/eejournal. Folks, it’s packed with all kinds of great tech videos, including our very popular Chalk Talk webcast series, hosted by me. And be sure you hit that subscribe button while you’re at it!

Thanks so much for tuning in today. If you know of any cool new technology, or heck, you just want to chat, shoot me a line at Amelia — that’s A-M-E-L-I-A — at eejournal.com, or post a comment on our forums on eejournal.

For the week of November 13th, 2026, I’m Amelia Dalton, and you’ve been fried!